1. Field of the Invention
This invention relates to the field of testers for integrated circuits. More specifically, the invention relates to a device to hold and align an integrated circuit within a tester.
2. Description of the Related Art
A chip is the smallest unit of fabrication in semiconductor technologies. A single chip normally contains multiple transistors that are connected into more useful entities known as logic gates. Complex chips have many logic gates, forming multiple logic circuits. Very Large Scale Integrated (VLSI) circuit chips, a class of chips with very dense circuitry, can host millions of transistors per chip, and can embody a number of computational devices on a single chip, including memories and microprocessors.
As presently fabricated, a chip is a thin (0.2 to 0.25 mm) piece of square or rectangular silicon encapsulated in an outer package. This package (for example, a dual inline package (DIP), a ball grid array package, a leadless carrier, or the like) provides pins that electrically connect the chip to its operating environment, normally a printed circuit board. The silicon chips are generally first fabricated as a matrix of dozens or even hundreds of dies that are etched on a large slice of silicon, termed a wafer. After fabrication, the wafer is diced and the individual dies are packaged into chips. Each die, while still on the wafer, includes electrical contacts that allow electrical signals to be input and output from the die circuitry.
VLSI chips must be tested both during the prototype stages of development and thereafter during mass production, to first verify the integrity of their design, and then to verify the quality of their manufacture. Testing can be performed either prior to or after packaging. Design verification systems have been developed that selectively excite the inputs of an integrated circuit chip with many input combinations, called test vectors. The outputs of the chip in response to the test vectors are checked for accuracy. For every test vector, there is an expected output, which is defined by the function performed by the electronic circuitry located within the chip. If there is a discrepancy between the expected output and the actual output when the circuit is presented with a specific test vector, there is likely a design error or, later, a manufacturing error in the chip. By testing a large number of input combinations, the likelihood that a design or manufacturing fault in the chip will pass undetected is significantly reduced, if not eliminated.
A typical design verifier used to test prototype chips includes a metallic chassis that holds the electronic circuitry necessary to test a chip, termed the device-under-test (DUT). The circuitry undergoing testing is typically mounted on a printed circuit board that electromechanically positions the integrated circuit device such that the pins of the chip can be connected to the test circuitry in the chassis. This circuit board, generally known as a DUT board, also functions to maintain a controlled impedance signal path from the test electronics to the chip pins. This is normally accomplished by providing paths of near equal length for electrical signal travel. The DUT board is also normally removable, so that removable connecting wires can be easily placed between the chip pins in the center of the board and the input/output (I/O) stimulus connections on the periphery of the board.
To ensure proper operation of a chip under a variety of conditions, tests are performed using a wide range of operating parameters. For example, the chip may be tested for over a wide temperature range. This change in temperature may cause thermal expansion or contraction of the device holding the chip on the tester. Further, operation of the chip itself generates heat, and this heat may also contribute to the thermal expansion of the device.
A typical design verifier holds a large number of chips in close proximity to one another. Because of slight changes in the relative positions of the connections between the DUT board and the test system, signal integrity with the DUT may be lost. Such differences may be caused by thermal expansion and retraction, machining tolerances, physical movement, or other factors. A system is needed that permits some variation between the DUT board and the test system with sacrificing signal integrity.
The invention enhances the ability of a DUT board to have slight variations from the test system. An assembly on the DUT board permits movement of a compliant contactor while maintaining a high level of signal integrity. The compliant contactor accepts a variety of different sized semiconductor devices along with a variety of different pinouts of the semiconductor devices. The compliant contactor includes an upper alignment block which receives the semiconductor device and a lower alignment block which contacts the contact pins of the tester. The upper alignment block may move within a predefined distance with respect to the lower alignment block to account for any tester movement, thermal expansion or contraction, or other factors. In an alternative embodiment, the compliant contactor may move in three directions with respect to the test board. In this embodiment, a contact pad provides electrical connection between a daughter card and the test board. The contact pad may be a compressible elastomeric connector.
One embodiment of the invention is a semiconductor contactor which holds and aligns semiconductors under test on a test board. The contactor comprises a contact housing having a plurality of contacts and being adapted to receive a semiconductor. An upper alignment block has a first plurality of pin apertures. An adaptor electrically connects the contacts on the contact housing to the pin apertures in the upper alignment block. A lower alignment block having a second plurality of pin apertures is positioned in coordination with the upper alignment block to align the pin apertures of the lower alignment block with the pin apertures of the upper alignment block. The aligned pin apertures receive a respective contact pin. The lower alignment block is fixed to the test board and is movable with respect to the upper alignment block to allow relative movement of the upper alignment block with respect to the lower alignment block. The aligned pin apertures have an enlarged region to permit movement of the contact pin within the aligned pin apertures when the upper alignment block moves with respect to the lower alignment block. The upper alignment block may be movably connected to the lower alignment block by a plurality of bearings. The bearings are positioned within retaining apertures of a set size which limits the movement of the upper alignment block. The upper alignment block may also be movably connected to the lower alignment block by a layer of slidable material. For example, in exemplary embodiments, the slidable material may be Teflon(copyright) or Nicotef.
Another embodiment of the invention is a semiconductor contactor which holds semiconductors under test on a test board comprising a daughter card having a first plurality of electrical contacts and a socket adapted to receive a semiconductor. The socket is attached to the daughter card. A resilient contact pad is positioned between the daughter card and the test board to electrically connect the electrical contacts on the daughter card to electrical contacts on the test board. A plurality of floating assemblies movably connect the daughter card to the test board and permit movement of the daughter card within a predefined range in relation to the test board. The resilient contact pad maintains electrical connection between the electrical contacts on the daughter card and the electrical contacts on the test board throughout the predefined range of movement of the daughter card.
Another embodiment of the invention is a method of holding a semiconductor device under test to a test board. The method comprises inserting the semiconductor device into a socket and movably attaching and electrically connecting an upper alignment block to a lower alignment block. The lower alignment block is secured to a test board. The invention further comprises electrically connecting the socket to the upper alignment block. An adaptor may be positioned between the upper alignment block and the socket. If included, the adaptor provides electrical connections between the upper alignment block and the socket.
Another embodiment of the present invention is a method of holding a semiconductor device under test to a test board. The method comprises movably attaching a daughter board to the test board. The daughter board is movable with respect to the test board within a predefined range in three dimensions. A socket is then connected to the daughter board, with the socket being adapted to receive the semiconductor device. A resilient contact pad is positioned between the daughter card and the test board to provide electrical connection from the daughter card to the test board throughout the predefined range of movement of the daughter card.
Another embodiment of the invention is a semiconductor contactor which aligns semiconductors under test on a test board. The semiconductor contactor comprises means for connecting a semiconductor and an upper alignment block having a first plurality of pin apertures. The semiconductor contactor also includes means for electrically connecting the semiconductor to the pin apertures in the upper alignment block. A lower alignment block has a second plurality of pin apertures positioned in coordination with the upper alignment block to align the pin apertures of the lower alignment block with the pin apertures of the upper alignment block to receive a respective contact pin in the upper and lower pin apertures. The lower alignment block is fixedly connected to the test board. Means for movably connecting the upper alignment block to the lower alignment block permit relative movement of the upper alignment block in relation to the lower alignment block. Also included are means for permitting movement of the contact pins within the aligned upper and lower pin apertures over the set degree of movement of the upper alignment block.
Another embodiment of the invention is a semiconductor contactor which holds semiconductors under test on a test board. The semiconductor contactor comprises a daughter card having a first plurality of electrical contacts and a socket adapted to receive a semiconductor. The socket is attached to the daughter card. Also included are means for electrically connecting the electrical contacts on the daughter card to electrical contacts on the test board and means for movably connecting the daughter card to the test board. The daughter card is movable within a predefined range with respect to the test board. Electrical connection is maintained between the electrical contacts on the daughter card and the electrical contacts on the test board throughout the predefined range of movement of the daughter card.
Another embodiment of the invention is an apparatus for connecting a semiconductor to a test board. The apparatus comprises a housing adapted to receive a semiconductor and a first section connected to the housing. A second section is connected to the test board. The first section is movable within a predefined range with respect to the second section. The second section maintains electrical connection between the first section and the test board throughout the predefined range of movement.